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	<title>application-specific-integrated-circuit &amp;laquo; WordPress.com Tag Feed</title>
	<link>http://en.wordpress.com/tag/application-specific-integrated-circuit/</link>
	<description>Feed of posts on WordPress.com tagged "application-specific-integrated-circuit"</description>
	<pubDate>Sun, 29 Nov 2009 03:48:12 +0000</pubDate>

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<title><![CDATA[Interview: Christine King of SMSC]]></title>
<link>http://geekgirlsnetwork.wordpress.com/2009/06/09/interview-christine-king-of-smsc/</link>
<pubDate>Wed, 10 Jun 2009 01:50:41 +0000</pubDate>
<dc:creator>geekgirlsnetwork</dc:creator>
<guid>http://geekgirlsnetwork.wordpress.com/2009/06/09/interview-christine-king-of-smsc/</guid>
<description><![CDATA[By @geekgirls During my sister’s college graduation this summer, I had the pleasure of listening to ]]></description>
<content:encoded><![CDATA[By @geekgirls During my sister’s college graduation this summer, I had the pleasure of listening to ]]></content:encoded>
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<title><![CDATA[Future Storage Systems: Part 3b - I/O Expansion Node]]></title>
<link>http://flickerdown.wordpress.com/2008/10/10/future-storage-systems-part-3b-io-expansion-node/</link>
<pubDate>Fri, 10 Oct 2008 16:00:17 +0000</pubDate>
<dc:creator>flickerdown</dc:creator>
<guid>http://flickerdown.wordpress.com/2008/10/10/future-storage-systems-part-3b-io-expansion-node/</guid>
<description><![CDATA[In Part 3a, we discussed the possibility of a purpose-driven Compute Node based on the Torrenza init]]></description>
<content:encoded><![CDATA[<div class='snap_preview'><p>In <a href="http://flickerdown.com/?p=139" target="_blank">Part 3a</a>, we discussed the possibility of a purpose-driven Compute Node based on the <a class="zem_slink" title="Torrenza" rel="wikipedia" href="http://en.wikipedia.org/wiki/Torrenza">Torrenza</a> initiative for the Future Storage system.  This expansion <a class="zem_slink" title="Node (computer science)" rel="wikipedia" href="http://en.wikipedia.org/wiki/Node_%28computer_science%29">node</a> made use of <a class="zem_slink" title="HyperTransport" rel="wikipedia" href="http://en.wikipedia.org/wiki/HyperTransport">Hypertransport</a> as a &#8220;glue&#8221; between the base storage compute node and the expansion node (of computation or I/O flavours) that could be added.  The advantages of that <a class="zem_slink" title="Network topology" rel="wikipedia" href="http://en.wikipedia.org/wiki/Network_topology">topology</a> were simple:  hot add support for additional processing power, additional I/O bandwidth within the system, and additional <a class="zem_slink" title="Computing" rel="wikipedia" href="http://en.wikipedia.org/wiki/Computing">computing</a> power for the array <a class="zem_slink" title="Operating system" rel="wikipedia" href="http://en.wikipedia.org/wiki/Operating_system">OS</a> (which we&#8217;ll cover in a later article).  In this overview, we&#8217;ll take a look at another variation on an expansion node: an I/O expansion node that will add additional front-end ports and/or functionality to the base system.  We will be referencing the diagram below. <em>(Apologies in advance for the image shearing off in the lower right hand corner)</em>.</p>
<div id="attachment_153" class="wp-caption aligncenter" style="width: 310px"><a href="http://flickerdown.com/wp-content/uploads/2008/10/htnodes-expansion-rev2-io.jpg"><img class="size-medium wp-image-153" title="Hypertransport I/O Expansion Topology" src="http://flickerdown.com/wp-content/uploads/2008/10/htnodes-expansion-rev2-io-300x219.jpg" alt="Hypertransport I/O Expansion Topology" width="300" height="219" /></a><p class="wp-caption-text">Hypertransport I/O Expansion Topology</p></div>
<p><!--more--></p>
<p>There are two different approaches that I&#8217;ll be taking a look at as part of this I/O expansion model: one approach is southbridge oriented with an additional southbridge providing additional <a class="zem_slink" title="PCI Express" rel="wikipedia" href="http://en.wikipedia.org/wiki/PCI_Express">PCIe</a> lanes; the other is looking at an I/O expansion model based on integrated <a class="zem_slink" title="Application-specific integrated circuit" rel="wikipedia" href="http://en.wikipedia.org/wiki/Application-specific_integrated_circuit">ASICs</a> and fixed optical ports that can provide connectivity to <a class="zem_slink" title="Fibre Channel" rel="wikipedia" href="http://en.wikipedia.org/wiki/Fibre_Channel">Fibre Channel</a>, <a class="zem_slink" title="Fibre Channel over Ethernet" rel="wikipedia" href="http://en.wikipedia.org/wiki/Fibre_Channel_over_Ethernet">FCoE</a>, and <a class="zem_slink" title="Image processing" rel="wikipedia" href="http://en.wikipedia.org/wiki/Image_processing">IP</a> technologies.  We&#8217;ll discuss both approaches separately and then dive into what each would look like practically (another diagram, I&#8217;m afraid).</p>
<div id="attachment_158" class="wp-caption aligncenter" style="width: 310px"><a href="http://flickerdown.com/wp-content/uploads/2008/10/htnodes-expansion-rev2-io-detail.jpg"><img class="size-medium wp-image-158" title="Hypertransport I/O Node - details" src="http://flickerdown.com/wp-content/uploads/2008/10/htnodes-expansion-rev2-io-detail-300x187.jpg" alt="Hypertransport I/O Node - details" width="300" height="187" /></a><p class="wp-caption-text">Hypertransport I/O Node - details</p></div>
<p>To begin, we&#8217;ll cover <strong>the SouthBridge model of I/O expansion</strong> (<em>left side of the diagram</em>).  In this particular model, the expansion module includes another southbridge device to cover the additional PCIe lanes required for either x8 or x4 slots.  The SouthBridge would be connected to the primary southbridge on the base node over the HT link.  Currently, many commercial systems are using this type of topology (using either PCIe between <a class="zem_slink" title="Logic gate" rel="wikipedia" href="http://en.wikipedia.org/wiki/Logic_gate">discrete logic</a> chips or another type of communication fabric like HT).  The southbridge(s), then, would provide discrete connectors to their own interfaces as well as maintaining system level consistency for I/O.  The <em>advantage </em>of this particular implementation would be the ability to utilize specific connectivity types (FCoE, FC, IB, IP, <a class="zem_slink" title="ISCSI" rel="wikipedia" href="http://en.wikipedia.org/wiki/ISCSI">iSCSI</a>) on the same type of pluggable cards as the base node (similar to Ultraflex on <a class="zem_slink" title="CLARiiON" rel="wikipedia" href="http://en.wikipedia.org/wiki/CLARiiON">EMC Clariion</a> CX4s).</p>
<p>The <strong>second variation on I/O expansion takes a different approach by integrating converged ASICs</strong> (cASIC) <strong>to handle I/O connectivity</strong> (<em>right side of the diagram</em>). This particular implementation has some obvious limitations from the start, namely, fixed port count, and limited fabric/topology support (IB is noticably lacking).  Additionally, the design would require more development and implementation work in order to support a passable physical implementation.  Limitations notwithstanding, there are some interesting integration points to look at.  <em>First</em>, the use of SFP+ or <a class="zem_slink" title="XFP transceiver" rel="wikipedia" href="http://en.wikipedia.org/wiki/XFP_transceiver">XFP</a> pluggables to support optical or electrical physical connectivity types assuages most of the fabric connectivity issues in addition to providing some level of forward-looking interoperability.  <em>Secondly</em>, the use of converged ASICs allows for multi-protocol encapsulation, encode/decode support that would support the aforementioned pluggables without having to retool or replace a PCIe module.  I&#8217;m assuming that some sort of protocol bit would need to be included in the SFP/XFP pluggables to enable the cASICs to &#8220;flip&#8221; from one protocol to another.  I believe that Qlogic and Emulex (and certainly Brocade/LSI) are implementing similar types of logic into their converged ASICs on their FCoE HBAs, so the next logical step would be said integration into a larger system.</p>
<p><strong>Closing Thoughts</strong></p>
<p>As always, I&#8217;m interested in your feedback and understanding on this (or any) subject I&#8217;ve written about so far.  We learn together and this particular posting is trying to dig deeper, probably past the point of my intelligence.  We&#8217;ll see&#8230;</p>
<p>Part 4 is still up for grabs as to what it will cover, but, most assuredly, it&#8217;ll probably be something to do with the Operating System for the FSS.  Stay Tuned!!!!!</p>
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<title><![CDATA[VLSI Design Engineer as a Career]]></title>
<link>http://vlsidesigner.wordpress.com/2008/08/15/vlsi-design-engineer-as-a-career/</link>
<pubDate>Fri, 15 Aug 2008 09:52:22 +0000</pubDate>
<dc:creator>vlsidesigner</dc:creator>
<guid>http://vlsidesigner.wordpress.com/2008/08/15/vlsi-design-engineer-as-a-career/</guid>
<description><![CDATA[What is VLSI ? Very-large-scale integration (VLSI) is the process of creating integrated circuits by]]></description>
<content:encoded><![CDATA[<div class='snap_preview'><p style="text-align:justify;"><strong><span style="color:#993300;">What is VLSI ?</span></strong></p>
<p style="text-align:justify;">Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistor-based circuits into a single chip. VLSI began in the 1970s when complex semiconductor and communication technologies were being developed. The microprocessor is a VLSI device.</p>
<p style="text-align:justify;">We have to thank VLSI, circuits that would have taken boardfuls of space can now be put into a small space few millimeters across!  This has opened new era.The things that were not possible before are made possible. VLSI circuits are everywhere &#8230; your computer, your car, your brand new state-of-the-art digital camera, the cell-phones, and what have you.</p>
<p style="text-align:justify;"><strong><span style="color:#993300;">VLSI Engineer as a Career</span></strong></p>
<p style="text-align:justify;">VLSI is also the fastest changing &#38; growing technology and it throws great career opportunities. VLSI design engineers are also in huge demand to develop FPGA implementations, ASICs and SoCs . Many people  don’t want to get stuck in routine software jobs,opt this as a  career.</p>
<p style="text-align:justify;">VLSI design is an extremely challenging &#38; creative job which  throws great opportunities for young engineers looking at  contributing to world-class Intellectual Property development. The most rewarding aspect of a career in VLSI design is,  advantage of a sense of ownership of what is developed. The  ability to get patents and the scope available for applied  research and publication make VLSI design engineer a dream  career for many engineers.</p>
<p style="text-align:justify;"><a title="VLSI engineer" href="http://www.jobsforuscitizens.com/job/31792/vlsi-design-engineer-san-jose-engineering.html" target="_blank"><span style="color:#0000ff;">Intrested in making exciting  career in VLSI ? If so  you are LUCKY, materialize your dream career as VLSI Engineer !!!</span></a></p>
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