Briefly, the key lessons are:

• You need a minimum die thickness of 50µm to handle local hot spots on the logic die. Otherwise the stacked DRAM die may receive too much heat from the logic die, which will degrade the DRAM’s storage-retention time.
• Experiments with the WIOMING design led to the creation of more than 40 new 3D-specific design rules and models.
• You will need clear agreements supply chain partners on a variety of parameters including ownership, liability, and value distribution for all 3D IC assemblies.
• Currently, the effort and expense involved with 3D design mandate a clear and convincing target application.

Partners involved in this work with Imec include: Globalfoundries, INTEL, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, Qualcomm, Xilinx, Altera, and Nvidia.

Read the full article on the Semiconductor Packaging News Web site here.

Note: EDA360 Insider covered this development last year. See “3D Thursday: IMEC prototypes 3D chip stack, finds some thermal surprises”

For previous EDA360 Insider coverage of this event, see “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?“

I am already registered. Hope to see you there.

“[Brion] Keller [senior architect at Cadence] noted that pre-bond testing is difficult for any die that is not intended to be the bottom die in a stack. Such dies only connect to the dies above or below through TSVs (where the TSVs touch down on micro-bumps on the neighboring die), and the resulting pins and micro-bumps are too small for current probe technology to handle.”

Here’s what Goering wrote about testing post-bonded 3D IC assemblies:

“During post-bond testing, the only contact you have with the package is through the package pins, and to access those you have to go through the bottom die.”

These factors are driving the quest to develop early standards for 3D IC die and assembly testing. All of this—especially the problems with probe access—seemed very, very familiar to me so I used Google to quickly find an editorial that I wrote and published in EDN back in early 1996, more than 15 years ago, when the IEEE 1149.1 test standard was still being adopted for board-level assemblies to combat the probe-access problems associated with surface-mount technology:

Design for test—or else. . .

Recently, I moderated an all-day design-for-test (DFT) seminar sponsored by Asset Intertech, National Semiconductor, and Synopsys. Odds are, you weren’t there. What follows are my opening remarks from the seminar, for your thoughtful consideration. If you have not looked at DFT methods in a while, this is a good time to do so. Design teams must use DFT methods, or they will quickly fall behind in today’s competitive markets.

“November 1995 marked the 10th anniversary of the development of boundary-scan standards. Back in 1985, Alcatel started the test-bus study group that became JTAG, or the Joint Test Action Group. Philips quickly took over the JTAG bandwagon and started driving it. JTAG hooked up with the IEEE’s P1149 serial-test-standard working group and the combined efforts eventually resulted in the 1149.1 standard.

“Surface-mount technology, with its fine component lead pitches and reduced pc-board geometries, has accelerated the problems of testability. Here’s what I wrote about testability in my Decade 90 series published seven years ago in EDN:

‘Many design engineers’ and managers’ attitudes about product testability seem to have frozen during an earlier era in electronics, when a technician could troubleshoot almost any problem in 20 minutes with a scope and a little savvy. For products designed without the design-for-testability philosophy, today’s most advanced in-circuit ATE testers can do no more than automate the time-honored tradition of sticking a test probe into a failing test node to find the problem. But as electronic systems grow in complexity, this approach grows less and less effective and increasingly costly.’

“In an epoch of world-shattering upheavals in electronic technology, it’s amazing how slowly some things change. Here’s what EDN’s test-and-measurement editor Dan Strassberg wrote about boundary-scan testing in his cover story published in October 1993:

‘As boards become increasingly dense, nodal-access problems of the kind once thought to be unique to multichip modules are affecting more and more boards. Boundary-scan testing is about the only game in town for overcoming these problems. But, like nearly every new technology, its acceptance has been hindered by a poorly developed infrastructure and, possibly, by a bit too much early optimism from partisans.’

“Our mission today is to convince you that much of that missing infrastructure is now developed, in the form of silicon, EDA tools, and test systems. You can and you should now be designing your products for testing.”

Like I said, it’s déjà vu all over again.

Here’s a photo of the chip stack:

The base chip is approximately 750µm thick. The two top components in the chip stack are each 25µm thick.

Here’s a close-up image of the stack edge:

This 3D integrated DRAM-on-logic demonstrator has already produced valuable data. For example, results indicate that a minimum die thickness of 50µm is required to deal with local hot spots on the logic die. Hot-spot temperatures run higher and are more confined locally as die thickness shrinks. Hot spots on the logic die also raise the local temperatures in the memory die, which can reduce DRAM retention time due to increased leakage from thermal effects. Imec’s 3D stacked demonstrator proved that the DRAM die will also act as an effective heat spreader for the logic die, which reduces the hot spot’s maximum temperature. The results of the various experiments allowed Imec to calibrate its 3D thermal models as implemented in associated 3D EDA tools.