TSMC tries to rally support for 450-mm wafers

Peter Clarke

EE Times

(05/10/2010 9:40 $ EDT)

LONDON — A transition to manufacturing on table-top sized 450-mm diameter wafers is an important enabler for cost reduction, according to Jack Sun, chief technology officer of Taiwan Semiconductor Manufacturing Co. Ltd., speaking at the International Electronics Forum, held in Dresden, Germany last week.

Unfortunately, despite saying that he expected 450-mm production to begin by the middle of the decade, Sun could shed no light on how the industry was going to fund what some observers have said could be a $20 billion bill.

“I do believe it is going to happen. No single company can afford it. It is an ecosystem issue; equipment makers, device makers, customers, governments all have to pitch in,” Sun said. “Before the [economic] crisis we thought it would happen in 2012,” said Sun. “Now that’s been pushed a couple of years out. We have to pick up the pace.” Unfortunately very few other chip makers — and almost none of the chipmaking equipment vendors — feel much inclined to help. The only companies expressing any interest in 450-mm wafer processing besides TSMC are Intel and Samsung.

Luc van den Hove, president and CEO of IMEC, said that expansion of the clean rooms at the European research institute could be used to aid progress towards 450-mm wafer production. “The expansion could be used for some early experiments but we are not going to set up a full 450-mm production line. I don’t see that happening in the next couple of years.”

Van den Hove stressed that the main reason for expansion was to accept a second preproduction extreme ultraviolet lithography tool. IMEC’s primary interest was in semiconductor process and device research and much of that could be done on 300-mm diameter wafers regardless of the size of wafer used in commercial production.

via EETimes.com – TSMC tries to rally support for 450-mm wafers.

Peter Clarke
EE Times
(05/10/2010 7:57 $ EDT)

Curte a vibe no seguinte link: clique aqui

Lumoza’s technology for screen printed electronics combines electroluminescent ink with a driver that controls the sequence and timing of the animation. The result is an electroluminescent computer animation that can be printed, just like ink, on all kind of surfaces, for example on a thin plastic foil. And afterwards, folded, rolled up, bended or wrapped.

The material used is a combination of a phosphor-based inorganic material and an organic material. The exact composition is confidential, “but it is not OLED”, the company states.

With its light-emitting screen, Lumoza aims at applications in the advertising and packaging market. The screen comes with a driver chip that also stores the animation data and is typically powered by a micro-battery, depending on the size of the installation. In order to save valuable battery energy, the chip contains a capacitive switch that activates the display when a prospective customer is approaching and deactivates it when he is moving on.

The process currently achieves pixels at a size of 200 micron, which yields a resolution of 127 pixels per inch. The animation content needs to be stored on the attached chip for the applications.

Not surprisingly the dvd-packaging industry has already shown interest, as they are always looking for new appealing packaging alternatives. The result is that the first foldable dvd-packaging with an electroluminescent animation is on show.

91202

Leveraging DfY for higher yield and reliability
Leveraging DfY for Time-to-Volume Acceleration
Infrastructure IP may require external support,
automated tools and equipment
Yield optimization loops leveraged at different
product realization steps during design, fabrication,
test and in-field
Collaborative Environment is necessary to achieve
Yield, Reliability and TTV goals

• DFM is a design flow issue!
• No single point solution, but a combination of methods
• Delicate trade-off throughout flow:
• Between avoidance and fix steps, and between other objectives
• Keep GDS2 sign-off levels alive in 45nm!
• Cannot afford loops that involve slow analysis
• Standard cells must remain rock-solid building blocks
• Wires layout patterns must be restricted
• 0-order DFM wisdom for synthesis tools:
• Bigger cells = better
• Lower density = better
• Keep it regular and uniform
• Must be 99.99% correct-by-construction
• … because iterative fixing is insecure and slow

Variability Aware Modeling has progressed in the past year
to a level that enable answering qualitative questions on
technology choices. We describe in detail the process to
predict system (IC) yield from technology variability, and
apply this to a concrete system under following
technology assumptions:
-low VTH, high VTH, and dual or triple VTH, when
assigning parts of the circuits or critical paths to one of
the VTH choices. Strategies on VTH assignment play a
role. Geometrical correlations of variability (local vs.
global, random vs. systematic) are taken into account,
thus leading to predictions of wafer to wafer and even
batch to batch variation of yield or process drift.
In a second, more speculative part we anticipate how this
framework can enable the design of system that tackle
variability with runtime countermeasures, such as course
grain and fine grains self-adaptive or centrally controlled
circuits

• DFM: For each solution proposed need to understand
• Designability and Manufacturability
• Improve design efficiency
• Improve model-to-hardware correlation
• Improve manufacturability
• What is being designed
• How and when ?
• What happened to design rules ?
• How do we get to a design methodology that works efficiently at 22nm ?

In collaboration with

CALIT Center of Advanced Learning in Information Technologies

Official CALIT website with abstract and calendar: http://www.imec.be/ovinter/static_training/CALIT.shtml

13 November 2007 TAD autumn seminar

IMEC auditorium

Kapeldreef 75

3001 Leuven, Belgium

The nanoelectronics and nanotechnology research center launches an industrial affiliation program on designing with emerging technologies.

By Suzanne Deffree, Managing Editor, News — Electronic News, 10/5/2009

IMEC today announced it has launched the industrial affiliation program (IIAP) INSITE (Integrated Solutions for Technology Exploration), a framework of design exploration modules that it said allows fabless and fab-lite companies, foundries, and EDA vendors to develop design and product information using emerging IC process technologies one to three generations ahead of IC manufacturing.

INSITE can be used to design in both IMEC’s emerging process technologies developed within its core CMOS research program and in more imminent foundry-level technologies targeted to early product development.

The INSITE program addresses two trends that IMEC said are creating a growing knowledge gap between the producers and users of digital CMOS technology: the move away from integrated design and manufacturing to separate chip foundries and fabless design houses, and the evolution toward more application-specific technology offerings as technologies need to be adapted to achieve the targeted chip specification as improved speed, power, area, and cost cannot be realized with the same technology.

“While the questions of fabless and fab-lite companies related to designing with emerging technologies are distinct from those of foundries, EDA companies and IP vendors, the solutions to their questions require collaboration and dialog between all parties,” Phillip Christie, principal researcher at IMEC, said in a statement. “INSITE will leverage IMEC’s extensive process technology knowledge and long tradition of working at the interface between technology and design. It will provide customized solutions for the exploration of design and technology trade-offs to all players in the semiconductor value chain.”

IMEC described the program as one set up as a modular and extensible framework that provides the required flexibility for the program partners. It comprises a design interface, circuit-level IP generation, and pathfinding.

The key competences of the framework are:
-An in-depth understanding of advanced process technologies and process integration;
-Fabrication and measurement of test circuits using IMEC’s 200-mm and 300-mm wafer facilities;
-A flexible design interface to quickly couple technology advances to design flows;
-The rapid implementation of circuit-level IP;
-Tools and flows for rapid design of pathfinding experiments.

IMEC said the design interface is fully compatible and shares the same standards as design interfaces from commercial foundries.

New technologies will be embedded into circuit level IP using industry-standard data formats to make certain that products can be synthesized using emerging technologies within standard design flows in a transparent way. For emerging technologies, IMEC said that the same library IP can be implemented as virtual libraries with limited layout information and imported into a design flow emulation environment for rapid scenario analysis.

In other news from IMEC, the nanoelectronics and nanotechnology research center last week claimed a major step toward 3D integration of DRAM on logic when it announced it and partners taped-out Etna, a new 3D chip integrating a commercial DRAM chip on top of a logic IC.

The potential efficiency might not sound breathtaking considering that the National Renewable Energy Laboratory and the Defense Advanced Research Projects Agency both announced last year that they had produced cells that achieved more than 40 percent efficiency in the lab. But lab efficiencies and production efficiencies are not the same thing, and the highest efficiencies for mass-produced solar cells hover around 22 percent. SunPower Corp., which introduced 22-percent efficiency monocrystalline cells in 2007, last year announced it had produced a prototype with 23.4 percent efficiency, which it expects to launch commercially next year.

RoseStreet thinks its new hybrid cell – which “marries low-cost nitride thin film with the massive infrastructure of silicon solar cells,” as CEO Bob Forcier said in the press release – could be cheaper than crystalline silicon cells. The nitride film, the same material used in solid-state lighting and blue lasers, enables the cells to make use of more of the light spectrum, Forcier told us.

The company plans to use a fabless model, manufacturing the cells through a partner, and also plans to license some of its technology, Forcier added. RoseStreet hopes to reach costs of less than $1.50 per watt, or 10 cents per kilowatt-hour, by 2014. The company plans to target applications with space constraints, such as industrial rooftops and mobile devices.

RoseStreet will certainly have competition. Other technologies are also racing toward higher efficiencies, with six companies – Suntech Power, Sunovia Energy Technologies, IMEC, Q-Cells, Fraunhofer Institute for Solar Energy Systems and Oerlikon – last week announcing world-record-breaking efficiencies for different types of crystalline silicon, thin film and multijunction solar cells.

And RoseStreet will have its work cut out. Many companies developing new technologies end up running into complications that result in delays. So far, at least, Forcier said he doesn’t foresee any problems with getting or processing the nitride material that it plans to use. “Nitrides are pretty pervasive in other parts of the world . . . so we see it as a scaleable technology on a worldwide basis,” he said. “We have no concerns about sourcing.”

In any case, it’s a good sign that the company expects to reach production next year. If RoseStreet really can reach such high efficiencies at a lower cost than conventional crystalline silicon, and can manufacture the cells in mass quantities, it should have no trouble finding a market.

The company has been developing higher-efficiency solar technology since at least 2004, when it licensed multiband technology from the Lawrence Berkeley National Laboratory. The company has formed partnerships with Los Alamos National Laboratory and Sumitomo Chemical Co., which also invested in RoseStreet.

The company already operates a 500-kW pilot line in Phoenix and last year launched a solar-cell development center in the same city. The company plans to seek more funding – technically its Series A round – in the first quarter of 2010, Forcier said.

The potential efficiency might not sound breathtaking considering that the National Renewable Energy Laboratory and the Defense Advanced Research Projects Agency both announced last year that they had produced cells that achieved more than 40 percent efficiency in the lab. But lab efficiencies and production efficiencies are not the same thing, and the highest efficiencies for mass-produced solar cells hover around 22 percent. SunPower Corp., which introduced 22-percent efficiency monocrystalline cells in 2007, last year announced it had produced a prototype with 23.4 percent efficiency, which it expects to launch commercially next year.

RoseStreet thinks its new hybrid cell – which “marries low-cost nitride thin film with the massive infrastructure of silicon solar cells,” as CEO Bob Forcier said in the press release – could be cheaper than crystalline silicon cells. The nitride film, the same material used in solid-state lighting and blue lasers, enables the cells to make use of more of the light spectrum, Forcier told us.

The company plans to use a fabless model, manufacturing the cells through a partner, and also plans to license some of its technology, Forcier added. RoseStreet hopes to reach costs of less than $1.50 per watt, or 10 cents per kilowatt-hour, by 2014. The company plans to target applications with space constraints, such as industrial rooftops and mobile devices.

RoseStreet will certainly have competition. Other technologies are also racing toward higher efficiencies, with six companies – Suntech Power, Sunovia Energy Technologies, IMEC, Q-Cells, Fraunhofer Institute for Solar Energy Systems and Oerlikon – last week announcing world-record-breaking efficiencies for different types of crystalline silicon, thin film and multijunction solar cells.

And RoseStreet will have its work cut out. Many companies developing new technologies end up running into complications that result in delays. So far, at least, Forcier said he doesn’t foresee any problems with getting or processing the nitride material that it plans to use. “Nitrides are pretty pervasive in other parts of the world . . . so we see it as a scaleable technology on a worldwide basis,” he said. “We have no concerns about sourcing.”

In any case, it’s a good sign that the company expects to reach production next year. If RoseStreet really can reach such high efficiencies at a lower cost than conventional crystalline silicon, and can manufacture the cells in mass quantities, it should have no trouble finding a market.

The company has been developing higher-efficiency solar technology since at least 2004, when it licensed multiband technology from the Lawrence Berkeley National Laboratory. The company has formed partnerships with Los Alamos National Laboratory and Sumitomo Chemical Co., which also invested in RoseStreet.

The company already operates a 500-kW pilot line in Phoenix and last year launched a solar-cell development center in the same city. The company plans to seek more funding – technically its Series A round – in the first quarter of 2010, Forcier said.

MARIVELES, Bataan—Despite the global economic slowdown, European and Japanese ship owners said they are committed to giving more funds to train more Filipino seafarers at least for the next few years.

Both the Japanese Seafarers’ Union, its manning counterpart, and the International Maritime Employers’ Committee (IMEC) said they will continue to support their hundreds of scholars at the Maritime Academy of Asia and the Pacific (MAAP), one of the country’s maritime schools, owned by the country’s largest seafarers’ labor group.

“Japanese ship owners are committed to assist MAAP and our cadets as best as we can. . . the JSU-IMMAJ [International Manning Managers Association of Japan] campus is an example of such commitment,” said Takao Manji, chairman of IMMAJ, at a ceremony at the start of MAAP’s 2009-2010 school year on Monday.

No figures were given as to how much it has committed to give, but starting this year, there were additional 250 students on top of the about 300 existing students in varying levels.

Japanese ship owners also gave half of the P500 million worth of new building and equipment inside MAAP’s campus in Kamaya Point.

All of the students in MAAP are scholars of their respective ship owners, hoping that this will solve the current shortage of officers on ocean-going vessels. With this setup, the employers can mold their would-be employee starting when the student enters the campus.

Students, however, will have to work with the company immediately after graduation.

On the other hand, IMEC, an organization mainly composed of European ship owners, have also increased their students from just 30 a year to about 180 at the start of this year in a dedicated campus in MAAP.

At the same time, IMEC also has 50 scholars studying at the University of Cebu.

Bob Goodall, trustee of the International Manning Training Trust (IMTT) and vice president of IMEC, said they also plan to increase that number to 250 by next year, matching those of the Japanese scholars.

Goodall said they are spending about $4.1 million a year for all of its cadets, and the figure will increase by next year if they decide to add more scholars.

“We have no plans as of yet to decrease our attention on the training of our work force.”

About 70 percent of crew onboard Japanese-flagged fleet are Filipino seafarers, while IMEC employs about 66,000 Filipino seafarers, the single- biggest nationality among its fleet.

South Korean chip maker Samsung has just signed off on a Memorandum of Understanding (MOU) with their prior collaborators, the IMEC, to jointly work on green technology for radio. IMEC is a huge nonotechnology research center in Beligium that has been working on “green radio” for years. The terms of the MOU cover research on communications technologies including cognitive reconfigurable radio baseband and millimeter-wave wireless. (FYI: “Cognitive radio” is the term used for integrated chips that adapt to environmental variables such as changes in frequencies, indoor/outdoor conditions, signal strength and movement.)

This should be a good fit. These two companies have been working together on various projects for quite some time now. The relationship began in 2004, when they partnered on sub-32-nm CMOS. Then, in 2005, they took on multi-mode multimedia research together. In 2007, ubiquitous embedded systems were the name of the game. I guess you could say they have history.

Gail Flower, a contributing editor at Electronic Design News (EDN), reports that the two companies not only have a shared history of collaboration, but also a common environmentalist background:

IMEC already has an established green radio program that supports major standards for wireless communications covering cognitive radios. [...]

Meanwhile, in March of this year, Samsung announced a shift towards green-oriented innovative products as a general plan to help increase sales. One product already introduced includes an ultra-slim LCD line using LED backlighting technology for HCTVs and using up to 40% less power than conventional TVs without the technology.

While a lot of the applications for this sort of research will be aimed at the mobile market, I can see definite advantages for radio at all levels. First, there is the fact that mobile is radio’s new frontier so most mobile research will end up benefiting broadcast radio tangentially. Second there is the fact that cognitive radio chips can be used for many things including making traditional radio (possibly even HD, as well) more reliable and thus more accessible.

Hats off to them, after all it’s not easy being green!

Photo courtesy of stonethestone, used under its Creative Commons license

Na wat e-mails en telefoons had ik dan toch eindelijk een e-mail adres vastgekregen van een persoon die me waarschijnlijk wat meer kon vertellen over de emotiemonitor.
Ik kreeg het e-mail adres van Lindsay Brown, iemand die werkte voor IMEC in Nederland.
Ik had gevraagd aan haar of het niet mogelijk was om een interview te doen over de emotiemonitor.

Dat was mogelijk, ik mocht kiezen om het via telefoon te doen of om naar Eindhoven te gaan om het interview af te nemen.
Ik heb voor het laatste gekozen, omdat het via de telefoon te onhandig was naar mijn mening.

Dinsdag 10 Maart om 10u. stond het interview gepland….

Gegroet
Hans

Vijf oktober was het weer open bedrijvendag in Vlaanderen.
Ik ben die morgend om 8 uur uit men bed gekropen en men vader meegenomen in den auto. Op weg naar IMEC in Leuven.

Wie IMEC niet kent: het is een onderzoekcentrum gespecialiseerd in nano-elektronica
Ideaal, want dat intresseert me gigantisch veel!

We kwamen daar rond 10uur aan, en er was gelukkig nog niet al te veel volk.
Onmiddellijk ingeschreven voor een rondleiding door het gebouw, en lans een cleanroom!!

Cleanroom mochten we uiteraard (verdomd jammer) niet letterlijk betreden, maar we mochten eens langs de bezoekersingang (een gigantische glazen muur ). Dus dat was ook al zeker de moeite om eens te kijken.

Verder stonden er in de inkomshal wat spin-off’s van IMEC, onder andere 1tje die wist te vertellen dat ze zo weinig mogelijk in VHDL doen en voor de rest op c of c++ steunen! Ik zal zijn artikel bij gelegenheid wel eens inscannen

Zeer leuk uitstapje, dingen die je niet iedere dag ziet.

Hopelijk zie ik ze later wel iedere dag

(naar aanleiding flipblog)

–edit–

Een artikel van de site van Easics (één van die spin-off’s) over het belang van c in een fpga-ontwikkelproces

–edit2–

Artikel in kwestie: