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Freescale demonstrates first-pass Kinetis L silicon at Design West (The conference formerly known as the Embedded Systems Conference)

Two weeks ago, ARM introduced its new low-end Cortex-M0+ 32-bit processor core. At the same time, Freescale announced that it was planning on introducing a new line of Kinetis “L” low-power microcontrollers based on the ARM Cortex-M0+ processor. 1,350 more words

EDA360

3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. 371 more words

Silicon Realization

ExtremeTech.com provides some lessons to be learned from the Google Nexus One smartphone’s system-level design and Android 4.0—Ice Cream Sandwich

Ryan Whitwam at ExtremeTech.com has written another insightful article on System Realization as it relates to the Google Nexus One smartphone’s supposed inability to run Ice Cream Sandwich (ICS), the latest and soon-to-be-introduced version of the Google Android OS. 223 more words

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3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)

Tuesday, Xilinx announced that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, 36 12.5Gbps GTX serial transceivers, and 1200 user I/O pins. 623 more words

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