# Design Recap

4-Option Example

```for Case in 0 to N-1

-- CaseBits is a concatenated signal from the iSelector input
Selectors(Case) <= THNN(CaseBits)

GatedCase0 <= TH22(Selectors(Case), iOptions(Case).DATA0)
GatedCase1 <= TH22(Selectors(Case), iOptions(Case).DATA1)
next Case

output.DATA0 <= TH1N(Gated00, Gated10, Gated20, Gated30, ...)
output.DATA1 <= TH1N(Gated01, Gated11, Gated21, Gated31, ...) 866 more words```
NCL

# Theory

Multiplexers are components that let you switch between different options for a signal. They take in some number of option values (usually a power of 2) and a selector. 398 more words

NCL

#### Using an NCL Register

In this post, I described what a NCL register is. I wanted to get a more practical understanding of what the register does and how different pipeline stages interact. 185 more words

NCL

# Design Recap

The circuit from my last post:

```oS.1:
TH12(
TH22(
TH13(iA.1, iB.1, iC.1), -- 1 <= NumBits
TH23(iA.0, iB.0, iC.0)), -- NumBits < 2
TH33(iA.1, iB.1, iC.1))); -- 3 <= NumBits

oS.0:
TH12(
TH33(iA.0, iB.0, iC.0), -- NumBits < 1
TH22(
TH23(iA.1, iB.1, iC.1), -- 2 <= NumBits
TH13(iA.0, iA.0, iA.0)); -- NumBits < 3

oC.1: TH23(iA.1, iB.1, iC.1) -- 2 <= NumBits

oC.0: TH23(iA.0, iB.0, iC.0) -- NumBits < 2… 662 more words```
NCL

# Theory

Like the Half Adder, a Full Adder counts it’s inputs. The full Adder counts three of them though. This to account for the carry in of the previous bit. 518 more words

NCL

#### NCL Register Implementation

See this post for the design of the NCL Register.

# Implementation

I implemented this module structurally, with a `for...generate` (you’ll find that I’m a big fan of generics if you keep up with the blog). 322 more words

NCL

See this post for the theory and design of the NCL Half Adder.

# Design Recap

Here’s the circuit design:

(simple version)

(optimized version)

The top two gates are THxor0 gates, the next is a TH34w22, and the last one is a TH22 gate. 584 more words

NCL